1. Field of the Invention
The present invention relates to a graphics processor comprising an array-organized memory in general and in particular to a graphics processor comprising an array-organized memory and a dynamically controllable barrel shifter for accommodating the transfer of variable sized memory arrays between a data processor and the memory.
2. Description of the Prior Art
In applicants' U.S. Pat. No. 4,773,044, issued Sept. 20, 1988, entitled ARRAY-WORD-ORGANIZED DISPLAY MEMORY AND ADDRESS GENERATOR WITH TIME MULTIPLEXED ADDRESS BUS and assigned to the assignee of the present application and an article entitled "A VLSI Architecture for Updating Raster-Scan Displays" by Satish Gupta and Robert F. Sproull, Computer Graphics, Volume 15, Number 3, August 1981, pp. 71-78, a graphics processor comprising an array-organized memory is disclosed.
In a graphics processor, graphics information displayed on a display screen is stored in a bit map. To change the graphics information displayed on the screen and the corresponding bits stored in the bit map, the bits are read from the bit map to a data processing unit in the graphics processor, processed and written back into the bit map.
Frequently, data displayed on a screen and/or stored in a bit map are referred to as comprising pixels. In reference to a display screen, a pixel is typically a single dot on the screen which may comprise one of a variety of colors and/or intensities. In referring to a bit map, a pixel may comprise a plurality of bits. In a bit map comprising a plurality of memory planes, a pixel typically comprises a bit from the same location in each of the planes.
In a processor having an array-organized bit map, each array of pixels on the screen is considered a word and each pixel in a word comprises one or more bits in a bit map, depending on the number of memory planes in the bit map. For example, a 64-pixel word comprises an array of 8 rows and 8 columns of bits in 1 plane in a bit map, a 16-pixel word comprises 4 rows and 4 columns of bits in each of 4 planes in a bit map, a 4-pixel word comprises 2 rows and 2 columns of bits in each of 16 planes in a bit map. For each size of display, there is a one-to-one relationship between the location of each array of pixels on the display and the corresponding bits in the bit map. For example, a 1K.times.1K bit map comprises 1024 rows and 1024 columns of pixels on a display or, in terms of an 8.times.8.times.1 array, 128 rows and 128 columns of 8.times.8.times.1 arrays. The boundaries of each array of pixels are commonly referred to as word boundaries.
At times it is desirable to modify graphic data displayed on a screen which crosses one or more of the word boundaries on the screen. In these cases, bits in two or more words in the bit map must be transferred between the bit map and the data processing unit. However, it is found that when the data is transferred between the bit map and the data processing unit, the bits become scrambled. The bits become scrambled due to the difference between where the pixels are located from a logical standpoint in the array as they appear on the screen versus the way the bits forming the pixels are located from a physical standpoint in the memory. For example, assume that a screen comprises a plurality of rows and columns of words wherein each word comprises an 8.times.8 array of pixels and that adjacent words in the top row of words on the screen are designated 1 and 2. Further, assume that an 8.times.8 array of the pixels comprised of a group of pixels A from word 1 and a group of pixels B from word 2 are read to the data processing unit for modification. If this is done without providing for the scrambling which naturally results when such a transfer takes place, the location of the pixels A and B will be reversed in the data processing unit.
As a further example, assume that the 8.times.8 array of pixels to be read to the data processing unit, in addition to pixels A and B from words 1 and 2, also comprises pixels C and D from the words located below words 1 and 2. In that case, not only is the location of the pixels A and B reversed in the data processing unit, but the location of the pixels C and D are reversed and the location of pixels A and B as a group and the pixels C and D as a group are reversed.
In order to accommodate the negative effects of pixel scrambling, i.e. the reversal of pixel groups as they are transferred between a data processing unit and a bit map in systems comprising 8.times.8 arrays of pixels as described above, the use of a barrel shifter has been proposed as disclosed in Gupta et al, supra.
In Gupta et al, to process an array of bits in a memory corresponding to an 8.times.8 array of pixels on a screen, a 64 bit input barrel shifter and a 64 bit output barrel shifter are disclosed. Each bit in the array is coupled to one of the 64 inputs of the barrel shifters on a one-to-one basis. In operation, each of the inputs is thereafter selectively coupled to one and only one of the shifters 64 outputs depending on the amount of rotation that is required as defined by the values of the parameters i and j described in the above-identified patent application where ##EQU1## x =the column address of a pixel on the screen y =the row address of a pixel on the screen
AWS.sub.x =the number of pixels in an array on the screen in the x direction PA1 AWS.sub.y =the number of pixels in on the screen in the y direction
The integer quantities x, y, AWS.sub.x and AWS.sub.y are predetermined quantities which are supplied by the operator and stored in the apparatus used for calculating i and j. The term "remainder" stands for the remainder resulting from dividing two integers.
While the Gupta et al type system is designed to handle the scrambling of pixels from 8.times.8 pixel arrays, there is no provision for handling different sized arrays. For example, there is no provision for handling 4.times.4 pixel arrays comprising 4.times.4.times.4 bit arrays or 2.times.2 pixel arrays comprising 2.times.2.times.16 bit arrays. Moreover, there is no provision for rotating bits between planes in such arrays.